FIG. 23 shows a conventional liquid crystal driving power supply device. As shown in FIG. 23, this power supply device has a drive circuit 100 and a plurality of output portions 102 provided in correspondence to loads in order to supply an electric potential to a segment/common capacitative load CS of a liquid crystal panel. The drive circuit 100 has a divider circuit 105 and an operational amplifier circuit 109. The operational amplifier circuit 109 has a plurality of operational amplifiers 104. The divider circuit 105 has resistors R1 to R6 which divide a voltage between a high potential for liquid crystal VDD and a low potential for liquid crystal VEE to generate potentials V1 to V5. The potentials V1 to V5 are supplied to the plurality of operational amplifiers 104 in the operational amplifier circuit 109. The operational amplifiers 104 feed the inputted potentials V1 to V5 as potentials V1' to V5' which are the same potential as the former to a power supply wiring 103. The power supply wiring 103 supplies the high potential for liquid crystal VDD and the potentials V1' to V5'. Capacitors C1 to C5 are connected to the wiring 103 on which the potentials V1' to V5' appear. The output portion 102 is connected to the power supply wiring 103. On the basis of select signals S0 to S5, either the high potential for liquid crystal VDD or the potentials V1' to V5' selected by transfer gates 108 are supplied as a high potential for liquid crystal VDD" or output voltages V1", V2", V3", V4" and V5" to the segment/common capacitative load CS through an external connection terminal 101. The operational amplifiers 104 are supplied with either voltage VN or VP from a reference power supply circuit 106 for operational amplifiers 10.
FIG. 24 is a circuit diagram showing an example of the specific construction of the reference power supply circuit for operational amplifiers 106 shown in FIG. 23. As shown in FIG. 24, a P-type MOS transistor 1, a resistor RA and an N-type MOS transistor 2 are connected in series between the high potential for liquid crystal VDD and the low potential for liquid crystal VEE. In the P-type MOS transistor 1 and the N-type MOS transistor 2, drain and gate are connected. Voltage VP and voltage VN are derived from opposite ends of the resistor RA.
FIG. 25 is a circuit diagram showing an example of the specific construction of the operational amplifier 104 shown in FIG. 23, particularly illustrating a P top-type circuit. As shown in FIG. 25, voltage VP is supplied to the gate of a P-type MOS transistor 30 and the gate of a P-type MOS transistor 35. Voltage V5 is supplied to the gate of a P-type MOS transistor 31. The sources of P-type MOS transistors 30 and 35 are connected to the high potential for liquid crystal VDD. The drain of the P-type MOS transistor 30 is connected to the sources of P-type MOS transistors 31 and 32. The sources of N-type MOS transistors 33, 34 and 36 are connected to the low potential for liquid crystal VEE. The gates of the N-type MOS transistors 33 and 34 are connected in common and connected to a connecting node between the drain of the P-type MOS transistor 32 and the drain of the N-type MOS transistor 34. The P-type MOS transistor 31 and the N-type MOS transistor 33 have their drains connected to each other, a connecting node of which is connected to the gate of the N-type MOS transistor 36. The drain of the P-type MOS transistor 35 and the drain of the N-type MOS transistor 36 are connected to each other, from the connecting node of which output voltage V5' is outputted. The output voltage V5' is fed back to the gate of the P-type MOS transistor 32. A capacitor for phase security CP for preventing oscillation of the operational amplifier is connected between the gate of the P-type MOS transistor 32 and the gate of the N-type MOS transistor 36. It is to be noted that the capacitor CP may be omitted.
FIG. 26 is a circuit diagram showing a further example of the operational amplifier 104 shown in FIG. 23, particularly illustrating an N-top type circuit. As shown in FIG. 26, voltage VN is supplied to the gate of an N-type MOS transistor 70 and the gate of an N-type MOS transistor 75. Voltage V1 is supplied to the gate of an N-type MOS transistor 71. The sources of the N-type MOS transistors 70 and 75 are connected to a low potential for liquid crystal VEE. The drain of the N-type MOS transistor 70 is connected to the sources of the N-type MOS transistors 71 and 72. The sources of P-type MOS transistors 73, 74 and 76 are connected to a high potential for liquid crystal VDD. The gates of the P-type MOS transistors 73 and 74 are connected in common and connected to a connecting node between the drain of the N-type MOS transistor 72 and the drain of the P-type MOS transistor 74. The drain of the N-type MOS transistor 71 and the drain of the P-type MOS transistor 73 are connected, a connecting node of which is connected to the gate of the P-type MOS transistor 76. The drain of the N-type MOS transistor 75 and the drain of the P-type transistor 76 are connected, from a connecting node of which output voltage V1' is outputted. This output voltage V1' is fed back to the gate of the N-type MOS transistor 72. A capacitor CN for phase security for preventing oscillation of the operational amplifier is connected between the gate of the N-type MOS transistor 72 and the gate of the P-type MOS transistor 76.
The use of the FIG. 25 circuit or the FIG. 26 circuit as the operational amplifier 104 depends on the potentials V1, V2, V3, V4 and V5 to be inputted and the characteristic of the amplifier. The operational amplifier circuit 109 includes those shown in FIG. 25 and FIG. 26 as the operational amplifier 104.
With the construction as described above, in the divider circuit 105 in the drive circuit 100, the resistors of resistors R1 to R6 are provided in series between the high potential for liquid crystal VDD and the low potential for liquid crystal VEE, and the portion between the high potential for liquid crystal VDD and the low potential for liquid crystal VEE is resistor-divided to thereby obtain the potentials V1 to V5. These voltages V1 to V5 are inputted into the respective operational amplifiers 104. Each of the operational amplifiers 104 has a configuration which is generally known as the voltage-follower type wherein their output is fed back to one terminal as shown in FIGS. 25 and 26. That is, the inputted potentials V1 to V5 are impedance-converted into the form of the potentials V1' to V5' which are exactly the same potential as the former and supplied to the power supply wiring 103. The potentials V1 to V5 and the potentials V1' to V5' are the same in the voltage as each other but different in the current supply capacity from each other. That is, the current supply capacity of the potentials V1 to V5 is determined by the resistance value of the resistors R1 to R6 constituting the divider circuit 105. On the other hand, in the latter, the current supply capacity of the potentials V1' to V5' is determined by the current supply capacity of the operational amplifier 104, and therefore, much more output currents are obtained. As the result, the power supply wiring 103 which receives output currents of the operational amplifiers 104 and the output portion 102 increase in the load drive capacity with respect to the external segment/common capacitative load CS. The high potential for liquid crystal VDD and the potentials V1' to V5' are selected on the basis of the select signals S0 to S5 in the output portion 102 and supplied to the segment/common capacitative load CS through the external connection terminal 101. Thereby, the load CS is charged and discharged to assume a predetermined voltage.
FIG. 27 is a timing chart for a description of the operation of the FIG. 23 power supply device. In FIG. 27, (A), (B), (C), (D) and (E) show a select signal S1, a select signal S4, a select signal S5, an operational amplifier current IOP which flows through the operational amplifier 104, and a voltage applied to the segment/common capacitative load CS from the external connection terminal 101 of the output portion 102, respectively.
Also as shown in FIG. 27, in the case where the select signals S1, S4 and S5 are sequentially inputted, the potentials V1", V4", V5" and V1" are successively outputted in correspondence to the select signals S1, S4 and S5 to the external connection terminal 101 in FIG. 23. At this time, the segment/common capacitative load CS connected to the external connection terminal 101 is charged and discharged to the aforementioned potentials. In this case, the operational amplifier current IOP of constant magnitude flows in the operational amplifiers 104 in FIG. 23. As the result, the segment/common capacitative load CS as the load is driven.
Since the conventional liquid crystal driving power supply device is configured as described above, there arises a difficulty in that the power consumption is large as will be described below. For example, as will be understood from FIG. 27, it is assumed that the voltage V1" is outputted from the external connection terminal 101 to the segment/common capacitative load CS through the transfer gate 108(1) in accordance with the select signal S1 on the basis of the output V1' from the operational amplifier 104(1). It is further assumed that the output V4" on the basis of the output V4' from the other operational amplifier 104(4) is outputted after time Tf in accordance with the select signal S4. It is assumed, substantially similar to the former, that the output V5" is changed to the output V1" after time Tr. During these times Tf and Tr, it is necessary for the operational amplifier current IOP to keep flowing in order to drive the load, but conversely, during time Ts at which the voltage such as the voltage potential V4' does not change but the output of the same voltage value keeps outputting, the operational amplifier current IOP keeps flowing. The current which flows during an unnecessary time, as just mentioned above, is so large that it cannot be disregarded, resulting in an increase of power consumption. On the other hand, in the case of a large liquid crystal panel or the like, the number of the segment/common capacitative load CS and the capacity increase. Because of this, the time Tf and the time Tr become longer, and it is necessary to shorten the times Tf and Tr. To this end, the operational amplifier current IOP, which is a current steadily flowing into the operational amplifier 104, is unavoidably made large, and in addition, the power consumption increases as a consequence.
Alternatively, there is contemplated a method in which the potentials V1 to V5 as outputs of the divider circuit 105 are directly coupled to the potentials V1' to V5' and the operational amplifier 104 which requires the operational amplifier current IOP is removed to reduce the current. That is, the resistance values of the resistors R1 to R6 are made small to thereby lower the output impedances of the potentials V1 to V5, and the output current supplied to the segment/common capacitative load CS can be made large. However, in the case of the semiconductor integrated circuit, if the resistors R1 to R6 are made too small, the unevenness in terms of the manufacture increases; and in addition, in the case where the resistors R1 to R6 are made of thin P-type or N-type diffusion resistant layers or the like, a modulation effect of the substrate caused by a semiconductor substrate arises. For this reason, for example, there is a problem in that, even if the resistor R1 were to have the value as expected, the resistor R6 would have an abnormally large value. That is, it is difficult to properly perform the management of resistance values to properly maintain the accuracy of the potentials V1 to V5. To overcome this difficulty, the resistance values of the resistors R1 to R6 may be made large, and the unevenness arising during the manufacture may be suppressed. However, if such measures are taken, the drive capacity unavoidably becomes small. Therefore, uses of devices which may employ large resistance values other than those for driving a liquid crystal panel for displaying a small watch which does not require much current and potential accuracy of V1 to V5 cannot be said to be a realistic selection. Therefore, it is essential for a large liquid crystal panel which has a large load capacity and requires a large drive capacity to have the operational amplifier 104 for impedance conversion.
In liquid crystal panels or the like, the segment/common which are two electrodes for determining the transmission (lighting) of light and non-transmission (unlighting) of light with respect to the liquid crystal is a capacity component as viewed from the semiconductor circuit for driving the load. The liquid crystal panels become larger and larger, and the liquid crystal voltage used therefor, the segment/common of the liquid crystal panel and so forth increase with the trend of larger panels. The consumption current required to display the liquid crystal panel depends upon f.multidot.C.multidot.V (frequency.times. Capacity.times.Voltage). Therefore, as the voltage and capacity that should be used with a trend toward larger liquid crystal panels become large, an increase of consumption current is brought forth.
Recently, personal computers, word processors and the like which have large liquid crystal panels are miniaturized and formed into a book-type. Thereby, they are convenient for being carried but have a problem in that the life of their power cells is short. That is, there is a great demand with respect to the reduction in the consumption of power of the liquid crystal panels.